Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).
Early MOSFET processes used one type of doping to create either positive or negative channel transistors. More recent designs, referred to as complementary MOS (CMOS) devices, use both positive and negative channel devices in complementary configurations. While this requires more manufacturing steps and more transistors, CMOS devices are advantageous because they utilize less power, and the devices may be made smaller and faster.
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide for a gate dielectric becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric in MOSFET devices. The term “high k materials” as used herein refers to a dielectric material having a dielectric constant of about 4.0 or greater.
High k gate dielectric development has been identified as one of the future challenges in the 2002 edition of International Technology Roadmap for Semiconductors (ITRS), incorporated herein by reference, which identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. For low power logic (for portable electronic applications, for example), it is important to use devices having low leakage current, in order to extend battery life. Gate leakage current must be controlled in low power applications, as well as sub-threshold leakage, junction leakage, and band-to-band tunneling.
To fully realize the benefits of transistor scaling, the gate oxide thickness needs to be scaled down to less than 2 nm. However, the resulting gate leakage current makes the use of such thin oxides impractical in many device applications where low standby power consumption is required. For this reason, the gate oxide dielectric material will eventually be replaced by an alternative dielectric material that has a higher dielectric constant. However, device performance using high k dielectric materials tends to suffer from trapped charge in the dielectric layer, which deteriorates the mobility, making the drive current lower than in transistors having silicon dioxide gate oxides, thus reducing the speed and performance of transistors having high k gate dielectric materials.
Another problem with using a high-k dielectric material as the gate electrode of a CMOS transistor is referred to in the art as a “Fermi-pinning” effect, which occurs at the interface of the gate electrode and gate dielectric material. Fermi-pinning is a problem that occurs in CMOS devices having both poly-silicon and metal gates. The Fermi-pinning effect causes a threshold voltage shift due to the increased charge caused by the Fermi-pinning effect. Fermi-pinning causes an asymmetric turn-on threshold voltage Vt for the two transistors of a CMOS device, which is undesirable.
In prior art CMOS transistor designs, the gate dielectric material used for the CMOS transistor was typically SiO2 or SiON and the gate electrode comprises polysilicon. A symmetric threshold voltage Vt for the PMOS device and the NMOS device of a prior art CMOS device was easily achievable using SiO2 or SiON as a gate dielectric material. For the PMOS device, the gate electrode was P-type, which was typically achieved by using polysilicon doped with boron (B) as the PMOS gate electrode material, as examples. For the NMOS device, the gate electrode was N-type, which was typically achieved by using polysilicon doped with phosphorous (P) as the NMOS gate electrode material, as examples.
However, when attempts are made to use hafnium-based dielectric materials, a high k dielectric material, for the gate dielectric material of a CMOS device, problems arise. For the NMOS device, polysilicon doped with P may be used as the material for the gate electrode, and an N-type gate is achievable, which is desired. However, for the PMOS device, if polysilicon doped with B, for example, is used for the gate electrode material, the hafnium-based gate electrode material interacts with adjacent materials, caused by Fermi-pinning, resulting in an N-type gate, which is ineffective for the PMOS device. An N-type gate on the PMOS transistor is undesirable: the PMOS device gate should be P-type to optimize the CMOS device performance and achieve a symmetric Vtp and Vtn. Thus, a CMOS device having an N-type gate electrode for the PMOS transistor has an asymmetric Vtn, and Vtp, due to the Fermi-pinning effect of the high k dielectric material. Efforts have been made to improve the quality of high-k dielectric films and resolve the Fermi-pinning problems, but the efforts have resulted in little success.
In electronics, the “work function” is the energy (usually measured in electron volts) needed to remove an electron from the Fermi level to a point an infinite distance away outside the surface. Work function is a material property of any material, whether the material is a conductor, semiconductor, or dielectric. The work function of a metal is fixed and cannot be changed unless the material composition is changed, for example. The work function of a semiconductor can be changed by doping the semiconductor material. For example, undoped polysilicon has a work function of about 4.5 eV, whereas polysilicon doped with boron has a work function of about 5.0 eV. The work function of a semiconductor or conductor directly affects the threshold voltage of a transistor when the material is used as a gate electrode.
In prior art CMOS devices utilizing SiO2 or SiON as the gate dielectric material, the work function can be changed or tuned by doping the polysilicon used for the gate electrode material. However, the Fermi-pinning caused by the use of high k gate dielectric materials as the gate dielectric pins or fixes the work function, so that doping the polysilicon gate material does not change the work function. Thus, a symmetric Vt for the NMOS and PMOS transistors of a CMOS device having a high k material for the gate dielectric cannot be achieved by doping polysilicon gate material, as in SiO2 or SiON gate dielectric CMOS devices.
Thus, what is needed in the art is a CMOS transistor device design and method of manufacturing thereof that has a high-k gate dielectric and a symmetric Vt for the p channel metal oxide semiconductor (PMOS) transistor and n channel metal oxide semiconductor (NMOS) transistor of the CMOS device.
Another problem that arises when high k materials are used for the gate dielectric of a CMOS device is a high voltage threshold Vtp for a PMOS device. It is desirable to lower the Vtp in some CMOS transistor designs.
Furthermore, if polysilicon is used as a gate material when high k materials are used as a gate dielectric, poly(polysilicon) depletion can occur between the gate dielectric and the gate. When the CMOS device is operated in an inversion mode, poly depletion causes an increase in the electrical equivalent gate oxide, e.g., by about 4 to 5 Angstroms. It is desirable for the gate capacitance to be relatively high for increased gate control. However, poly depletion decreases the capacitance and lowers the drive current of the CMOS device, which is undesirable. Therefore, it would be advantageous to use metal as a gate material, to avoid the poly depletion effect. However, introducing metal as a gate material can cause integration problems in the manufacturing process. Many metals are not compatible with CMOS technologies, for example.